AR# 60846

MIG 7 Series DDR3 - Kintex-7 -2L/-3L - Incorrect refclk frequency of 400MHz generated for designs operating above 1333 Mbps (667MHz) causes DRC error during implementation

描述

Version Found: MIG 7 Series v2.1
Version Resolved: See (Xilinx Answer 54025)

Starting with v2.1, MIG 7 Series uses an increased IDELAYCTRL reference clock frequency for designs operating above 1333Mbps.  

See (Xilinx Answer 60687) for details. 

However, for Kintex -2L/-3L speed grades, a 400MHz reference clock is not supported.  

Therefore, a DRC error is generated during implementation as follows:

ERROR: [Drc 23-20] Rule violation (AVAL-31) IODELAY_RefClkFreq - Invalid configuration.
IDELAYE2_FINEDELAY u_mig_7series_v2_1/u_mig_7series_v2_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 has an invalid REFCLK_FREQUENCY value (400.000000).
Only values from 190-210 or 290-310 are allowed for this device and speedgrade.
A higher speedgrade and non-low-power device allows value ranges 190-210, 290-310, or 390-410.
Resolution: Change the timing requirements or look at the data sheet for the speedranges for other parts.

解决方案

To work around this, the parameter REF_CLK_MMCM_IODELAY_CTRL needs to be manually set to "FALSE" within the <module_name>_mig.v/.vhd and <module_name>_mig_sim.v/.vhd rtl files located within the user_design/rtl directory.  

This will keep the pre-existing 200MHz refclk setting.

Revision History:

06/18/2014 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 60846
日期 06/26/2014
状态 Active
Type 已知问题
器件
IP