AR# 60847


MIG 7 Series Multi-Controller - For designs with the Reference Clock set to "Use System Clock", the rtl has ref_clk connected to the last controller's input clock regardless of which controller input clock is set to 200MHz


Version Found: v2.1
Version Resolved: See (Xilinx Answer 54025)


For multi-controller MIG 7 Series designs where at least one controller has an input clock period set to 5000 ps (200 MHz), the Reference Clock option can be set to the "Use System Clock" setting. 

When this is set, the MIG rtl should connect the reference clock signal "clk_ref_in" to the 200 MHz input clock.

However, in the generated user design rtl top file (<module name>_mig and <module name>_mig_sim modules), the clk_ref_in is set to the input clock for the last configured controller within the MIG tool.  

This means that if three controllers are generated, C0, C1, and C2, the rtl will always connect C2's input clock to clk_ref_in regardless of which controller has the 200MHz input clock.

This connection may result in the IDELAYCTRL not being clocked at the appropriate frequency and may result in timing violations.


Within the <module name>_mig and <module name>_mig_sim modules located in the user_design/rtl directory, the following rtl assigns the clk_ref_in connection:
          assign clk_ref_in = c2_mmcm_clk;
          assign clk_ref_in = clk_ref_i;
However, c2_mmcm_clk may not be the 200MHz input system clock. 

Manual modification to this section of rtl is required to connect the appropriate 200MHz input clock to "clk_ref_in".

Revision History:
06/04/2014 - Initial Release

AR# 60847
日期 06/11/2014
状态 Active
Type 已知问题
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