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AR# 60895

LogiCORE IP AXI Video Direct Memory Access - How does the VDMA pack and unpack data if the AXI4-Stream write (S2MM) and read (MM2S) are different widths?

描述

How does the VDMA pack and unpack data if the AXI4-Stream write (S2MM) and read (MM2S) are different widths?

解决方案

The VDMA attempts to pack data as efficiently as possible. 

As a result when it packs the data it uses 2 2/3 pixel packing. 

When the VDMA unpacks, it does a simple unpacking and just reads back the data.

The results will look like this:

VDMA write (S2MM) side:
    AXI-S interface 24-bit: | R0 | B0 | G0 |
    AXI-S interface 24-bit: | R1 | B1 | G1 |
    AXI-S interface 24-bit: | R2 | B2 | G2 | These 3 beats are combined like this to make 1 beat on the MM interface:
     MM interface 64-bit:  | B2 | G2 | R1 | B1 | G1 | R0 | B0 | G0 |

VDMA read (MM2S) side:
     MM interface 64-bit:  | B2 | G2 | R1 | B1 | G1 | R0 | B0 | G0 |
    AXI-S interface 24-bit: | B2 | G2 | R1 | B1 | G1 | R0 | B0 | G0 | This would be a 1 to 1 beat since the interfaces are the same.
 

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AR# 60895
日期 08/25/2014
状态 Active
Type 综合文章
IP
  • AXI Video Direct Memory Access
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