AR# 61063

Vivado HLS 2014.2: Debug Guide for investigating C/RTL co-simulation issues

描述

The Vivado HLS C/RTL co-simulation feature uses the user C test bench and generated RTL to confirm that the RTL simulation matches the behavior of the C, C++ or SystemC source code.

When the C/RTL co-simulation fails, the following message is issued.

@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***

This Answer Record contains a downloadable PDF with steps to investigate and a debug guide for use when there is an issue with the Vivado HLS C/RTL co-simulation flow.

解决方案

Answer Records are Web-based content that are updated as new information becomes available.

To obtain the latest version of the PDF, visit this answer record.

Revision History

09/09/2014 Initial Release

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附件

文件名	文件大小	File Type
Vivado HLS: Debug Guide for investigating C/RTL co-simulation issues	467 KB	PDF

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主要问答记录

Answer Number	问答标题	问题版本	已解决问题的版本
47431	Xilinx Vivado HLS Solution Center - Design Assistant	N/A	N/A

AR# 61063
日期	09/09/2014
状态	Active
Type	解决方案中心
Tools	Vivado Design Suite - 2014.2 Vivado Design Suite Vivado Design Suite - 2014.1

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AR# 61063

Vivado HLS 2014.2: Debug Guide for investigating C/RTL co-simulation issues

描述

解决方案

附件

链接问答记录

主要问答记录