AR# 61224

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Aurora 8B10B v10.2 - Latches inferred in CRC module

描述

The following warning is reported with an Aurora 8B10B v10.2 core when the CRC module is enabled:

WARNING: [Synth 8-327] inferring latch for variable 'msg_reg' for crc_top.vhd

This issue is applicable only for vhdl cores. 

This Answer Record provides the required edits to avoid latches being inferred in the CRC module.

解决方案

Combinational logic present in the CRC_GEN process statement does not contain an else statement causing latches to be inferred in crc_top.vhd.

The code changes below should be made to resolve this issue.

1)

Original code 

CRC_GEN: process(crcreg, CRCIN, data_width,data_in_8,data_in_16, data_in_24,data_in_32)

    variable   msg        :  std_logic_vector(40 downto 0);

    variable   concat_data_8 :  std_logic_vector(31 downto 0);

    variable   concat_data_16 :  std_logic_vector(31 downto 0);

    variable   concat_data_24 :  std_logic_vector(31 downto 0);

    variable   concat_data_32 :  std_logic_vector(31 downto 0);

begin


Replacement code

CRC_GEN: process(crcreg, CRCIN, data_width,data_in_8,data_in_16, data_in_24,data_in_32,zero_8,zero_16,zero_24,poly_val)

    variable   msg            :  std_logic_vector(40 downto 0) := (others => '0');

    variable   concat_data_8  :  std_logic_vector(31 downto 0) := (others => '0');

    variable   concat_data_16 :  std_logic_vector(31 downto 0) := (others => '0');

    variable   concat_data_24 :  std_logic_vector(31 downto 0) := (others => '0');

    variable   concat_data_32 :  std_logic_vector(31 downto 0) := (others => '0');

begin

2)

Original code

elsif (data_width = "11") then


Replacement code

else



Revision History:
08/04/2014 - Initial Release


AR# 61224
日期 08/07/2014
状态 Active
Type 综合文章
器件
Tools
IP
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