AR# 61229

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Aurora 64B66B/Aurora 8B10B - Ultrascale GTH - CPLL Duplex designs do not have lane_up/channel_up asserted in hardware.

描述

When an Aurora 64B66B/Aurora 8B10B design is created with CPLL configuration, the INIT_CLK frequency can be any value between 6.25Mhz to line_rate/64 or 200Mhz for Aurora 64b66b or line_rate/<internal datapath width> or 200Mhz for Aurora 8b10b, whichever is lower.

If the INIT_CLK frequency is chosen as anything outside of the above determined values, lane_up/channel_up are not asserted high on the board.

解决方案

To resolve this issue, update the C_FREERUN_FREQUENCY parameter with the exact frequency in the <user_component_name>_gt/synth/<user_component_name>_gt.v file inside the IP folder.


Revision History:
06/23/2014 - Initial Release
AR# 61229
日期 06/23/2014
状态 Active
Type 综合文章
器件
IP
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