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AR# 61295

MIG 7 Series RLDRAMII - For x36 designs the QK/QK# clocks capture the wrong data byte groups

描述

Version Found: MIG 7 Series v2.0 Rev 2
Version Resolved: See (Xilinx Answer 54025)

For x36 components QK0/QK#0 are edge aligned with DQ0-DQ17 and QK1/QK#1 with DQ18-35.

However, in some configurations MIG has this alignment swapped which can cause hardware failures due to trace length mismatch and edge misalignment.

解决方案

This can be fixed by modifying the top-level pinout parameters of MIG.

Below is an example of the parameters and how to change the CPT_CLK_SEL_B# parameters:

   parameter CPT_CLK_SEL_B0  = 32'h11_11_12_12,
Should be changed to:
   parameter CPT_CLK_SEL_B0  = 32'h12_12_11_11,

Revision History
06/16/2014 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 61295
日期 07/01/2014
状态 Active
Type 已知问题
器件
IP
的页面