With Aurora 8B10B v10.1, latches can be inferred for the variable 'storage_31_reg'.
The Following warning message is received:
[Synth 8-327] inferring latch for variable 'storage_31_reg'
This issue applies to VHDL cores only.
This answer record provides the updates required to avoid this behavior.
The "storage_31_reg" signal is not initialized while declaring it.
Please initialize this signal to '0' as shown below to avoid latches being inferred.
signal storage_31 : std_logic_vector(0 to 5) := "000000";
08/04/2014 - Initial Release