AR# 61402

7 Series Integrated Block for PCI Express v3.0 (Rev2) - PCIe x8Gen2 PIO example design for k70tfbg676-2 device fails in timing

描述

Version Found: v3.0 (Rev2)
Version Resolved and other Known Issues: See (Xilinx Answer 54643)

When generating the x8Gen2  7-Series Integrated Block for PCI Express v3.0 (Rev2) core for an xc7k70tfbg676-2 device, the PIO example design fails in timing.

解决方案

To work around this issue, enable pipelining registers by setting the following parameters to '1' in the pcie_7x_0_core_top.v file:

  • TL_RX_RAM_WRITE_LATENCY
  • TL_TX_RAM_WRITE_LATENCY
  • TL_RX_RAM_RADDR_LATENCY
  • TL_TX_RAM_RADDR_LATENCY

This will be fixed in a future release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
07/07/2014 - Initial Release 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54643 7 Series Integrated Block for PCI Express — Vivado 2013.1 及更新工具版本的发布说明及已知问题 N/A N/A
AR# 61402
日期 07/08/2014
状态 Active
Type 已知问题
IP