AR# 61492: UltraScale FPGA Gen3 Integrated Block for PCI Express - I/O Standard selection for PERSTn pins
UltraScale FPGA Gen3 Integrated Block for PCI Express - I/O Standard selection for PERSTn pins
What I/O standard should be used for PERTSn pins in UltraScale devices?
The voltage level of the FPGA I/Os must match the voltage level of the I/O bank for the FPGA.
If this voltage level is different from the voltage level required on the PCIe edge connector then an external level shifter must be used.
For the KU105 the bank voltage of the PERSTN0/1 pins is set to 1.8v. The 1.8v signal then passes through a level shifter to get to a 3.3v signal as required by the PCIe spec.
The same is true for the VU107 board. VU devices also have the PERSTn0/1 pins on HPIOBs which are not capable of 3.3v.
LVTTL is an unsupported standard for these I/Os. External level shifters must be used as is done with the KU105 and VU107 development boards.
If the use of an external level shifter is undesirable the PCI Express edge connector reset pin must be moved to a 3.3v capable I/O bank within the FPGA and the "Use the dedicated PERSTN routing resources" option must be disabled in the Advanced settings of the IP customization GUI.
Revision History: 15/07/2014 - Initial Release
UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)