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AR# 61624

2014.2 - Vivado IP Integrator - Board Automation flow for MIG on an AC701 board picks incorrect sys_clk Pins.


If I select the Board Automation flow on an IP Integrator design containing a MIG IP, the board will pick an incorrect sys_clk pin.

How can this be addressed?


To work around this issue, run the block automation once. Then re-customize the MIG IP.

In the customize GUI, assign the sys_clk pins to R3/P3 instead of N3/N2.


AR# 61624
日期 07/28/2014
状态 Archive
Type 综合文章
  • Vivado Design Suite - 2014.2
Boards & Kits
  • Artix-7 FPGA AC701 Evaluation Kit