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AR# 6164

8.1i Floorplanner - The IBUFG placement is not verified by DRC check

Description

Keywords: Virtex, CLKDLL, 2.1i, 3.1i, 4.1i, 5.1i, 6.1i, 7.1i

The Floorplanner DRC does not verify the IBUFG placement. If the IBUFG is placed in the wrong location, MAP fails with the following error:

"ERROR:xvkpu - The symbol clk.pad failed to join a global clock I/O component as required. The symbol has a constraint (LOC=B0) that specifies an illegal physical site for the component."

解决方案

Please refer to the Virtex Data Sheets for the correct IBUFG locations:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families&iLanguageID=1

Alternatively, the following information indicates the IBUFG locations (per package):

CS144: K7, M7, A7, A6
TQ144: 90, 93, 19, 16
PQ240/HQ240: 92, 89, 210, 213
BG256: Y11, Y10, A10, B10
BG352: AE13, AF14, B14, D14
BG432: AL16, AK16, A16, D17
BG560 : AL17, AJ17, D17, A17
FG256: N8, R8, C9, B8
FG456: W12, Y11, A11, C11
AR# 6164
创建日期 08/21/2007
Last Updated 06/17/2008
状态 Archive
Type 综合文章