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AR# 61696

UltraScale/UltraScale+ Memory IP - The funcsim.v/.vhdl structural simulation model is not supported

描述

Version Found: v5.0 Rev1

Version Resolved: See (Xilinx Answer 58435)

MIG only supports behavioral simulations and does not support structural (i.e. gate-level) simulations of any kind.

However, when using the Out-Of-Context (OOC) flow, the <IP_name>_funcsim.v/.vhdl output products are still generated.

This can be misleading and will cause simulation failures if the <IP_name>_funcsim.v/.vhdl model is used.

解决方案

Because only behavioral simulations are supported, the structural model should not be used.

This can be avoided by only running behavioral models or by manually compiling the MIG IP RTL when combining with structural models used by other IP.

Revision History

08/05/2014 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 61696
日期 12/21/2017
状态 Active
Type 已知问题
器件 More Less
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