AR# 61744


MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware when targeting Vivado 2014.2. Errors were not seen in previous versions.


Version Found: MIG v2.1
Version Resolved: See (Xilinx Answer 54025)

When running a DDR3 interface with ECC enabled in hardware, multiple ECC errors are issued. 

These are errors that were not seen in previous versions.


This is a known issue with the ECC generation rtl . 

A change in the Vivado 2014.2 tools resulted in a different rtl optimization that uncovered the rtl issue.  

To work around the issue, replace the mig_7series_v2_1_ecc_gen.v module generated by MIG with the module attached to this answer record.  

This rtl file is located in the "core_name\user_design\rtl\ecc" directory.

Note: When rtl updates are made, out-of-context (OOC) synthesis must be disabled.

Revision History:
08/29/2014 - Initial Release


文件名 文件大小 File Type
mig_7series_v2_1_ecc_gen.v 7 KB V
AR# 61744
日期 09/16/2014
状态 Active
Type 已知问题
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