AR# 61790


7 Series MIG - DDR3 - app_rd_data_end stays high


Version Found: MIG 7 Series v2.1
Version Resolved: See (Xilinx Answer 54025)

After toggling a number of times, app_rd_data_end may become stuck high as shown in the example design simulation below:



With controllers using a 4:1 PHY to controller clock ratio, app_rd_data_end is always asserted high along with app_rd_data_valid.

Hence this signal is not needed for user logic and can be ignored. 

For 2:1 controllers, app_rd_data_end does toggle properly on the second word returned on app_rd_data.

Revision History

11/24/2014 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 61790
日期 01/09/2015
状态 Active
Type 已知问题
People Also Viewed