MIG 7 Series LPDDR2 designs running at 200MHz may see hardware failures during the Phase Detection stage of calibration.
This is due to phase difference between the memory reference clock and DQS input strobe when they are at equal frequencies.
This makes edge detection unreliable.
If hardware failures are seen during the Phase Detection stage of calibration, increase the memory operating frequency to 220MHz or higher.
This issue will be fixed in a future release of the IP.
09/09/2014 - Initial Release