AR# 61901

UltraScale DDR3/DDR4 - memory model violations observed during simulation

描述

Version Found: DDR4 v5.0 (Rev. 1), DDR3 v5.0 (Rev. 1)

Version Resolved: See (Xilinx Answer 69035) for DDR4, (Xilinx Answer 69036) for DDR3

The following violations might be observed when simulating MIG UltraScale DDR3/DDR4 designs:

DDR3:

# sim_tb_top.mem_model_x8.memModel[2].u_ddr3_x8: at time 0.0 ps ERROR: tIPW violation on CKE by 560.0 ps
# sim_tb_top.mem_model_x8.memModel[2].u_ddr3_x8.reset: at time 0.0 ps ERROR: CKE must be inactive when RST_N goes inactive.
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 2720347.0 ps ERROR: tIS violation on CKE by 170.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3044963.0 ps ERROR: tIS violation on BA 1 by 170.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3044963.0 ps ERROR: tIS violation on ADDR 3 by 170.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 4385315.0 ps ERROR: CAS Latency = 10 is illegal @tCK(avg) = 1308.937500
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 4385315.0 ps ERROR: CAS Latency = 10 is not valid when CAS Write Latency = 8

DDR4:

tWR/tRTP SPEC_VIOLATION tWR spec:12 loaded:10 tRTP spec:6250 loaded:6250 @4835815

解决方案

These violations are safe to ignore as no calibration has been completed yet.

Once calibration has completed these violations should be resolved.

Revision History

09/02/2014 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 61901
日期 12/21/2017
状态 Active
Type 已知问题
器件
Tools
IP