Version Found: DDR4 v5.0, DDR3 v5.0
The LogiCORE IP Architecture UltraScale Based FPGAs Memory Interface Solutions (PG150) currently states the following pin rule for DDR4/DDR3:
"* reset_n can only be allocated within the memory interface banks"
Previous MIG generations allowed the reset_n pin to be placed anywhere within the FPGA as long as timing was met.
Why has this changed?
This limitation on reset_n will be lifted in a future release.
The same rule of allowing reset_n to be allocated to any FPGA pin so long as timing is met will be supported.