Version Found: DDR4 v5.0, DDR3 v5.0
Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3
The LogiCORE IP Architecture UltraScale Based FPGAs Memory Interface Solutions (PG150) currently states the following pin rule for DDR4/DDR3:
"* reset_n can only be allocated within the memory interface banks"
Previous MIG generations allowed the reset_n pin to be placed anywhere within the FPGA as long as timing was met.
Why has this changed?
This limitation on reset_n will be lifted in a future release.
The same rule of allowing reset_n to be allocated to any FPGA pin so long as timing is met will be supported.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 69036 | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues | N/A | N/A |
| 69035 | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues | N/A | N/A |
| AR# 62050 | |
|---|---|
| 日期 | 12/21/2017 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| IP | |