This answer record includes a debug guide for power and signal integrity board level issues. It details how to accurately measure or quantify these issues based on the failing behavior.
It also provides best practices, checklists, and methods for resolving or mitigating different types of power or signal integrity issues.
It includes focused chapters on debugging hardware related issues with memory interfaces and high speed Serial I/O (HSSIO) interfaces.
This debug guide is to be used by anyone working to resolve Xilinx FPGA or SoC related signal or power integrity issues.
The material here is considered additional or supplemental to the Xilinx user guides and is not meant to replace them as such.
The debug guide attached to this answer record is structured as follows:
Introduction.
Chapter 1: Power Supplies
Chapter 2: Signal Integrity on Critical Nets
Chapter 3: Debugging SSO Noise and Cross-Talk Issues
Chapter 4: Debugging Jitter Issues
Chapter 5: Debugging Memory Interface Issues, Additional Considerations
Chapter 6: Debugging High-Speed Serial Interfaces, Additional Considerations
| 文件名 | 文件大小 | File Type |
|---|---|---|
| Hardware_Debug_Best_Practices.pdf | 3 MB |