AR# 62265


AXI Memory Mapped to PCI Express v2.5 - Incorrect default clock placement for KC705 Board


Version Found: v2.5
Version Resolved and other known issues: (Xilinx Answer 54646)

When using the AXI Memory Mapped to PCI Express v2.5 core example design for a KC705 board, it will not link up due to incorrect clock placement.


To fix the issue, locate the top level design constraint file (usually named xilinx_axi_pcie_7x_ep_<link_config>_<blk_locn>.xdc) 

Replace the following constraint:

set_property LOC IBUFDS_GTE2_X0Y3 [get_cells refclk_ibuf]


set_property LOC IBUFDS_GTE2_X0Y1 [get_cells refclk_ibuf]

Revision History:
10/06/2014 - Initial Release

AR# 62265
日期 10/08/2014
状态 Active
Type 综合文章
Boards & Kits
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