AR# 62375


LogiCORE IP Serial RapidIO Gen2 v3.2 - HELLO Format support in example design simulation


Version Found: 3.2

Version Resolved and other Known Issues: (Xilinx Answer 54648)

During example design simulation, when Initiator/Target Legacy is chosen as the Port I/O Style, the tool returns the following error message:

# ** Fatal: (vsim-3363) ./../../../srio_no_hello_msg_default_example.srcs/sources_1/ip/srio_no_hello_msg_default/synth/srio_no_hello_msg_default_block.v(945): The array length (8) of VHDL port 's_axis_iotx_tuser' does not match the width (32) of its Verilog connection (11th connection).
#    Time: 0 ps  Iteration: 0  Instance: /srio_sim/srio_example_top_primary/srio_no_hello_msg_default_inst/inst/srio_no_hello_msg_default_block_inst/srio_gen2_v3_2_unifiedtop_inst File: ./../../../srio_no_hello_msg_default_example.srcs/sources_1/ip/srio_no_hello_msg_default/srio_gen2_v3_2/hdl/srio_gen2_v3_2_unifiedtop.vhd Line: 187
# FATAL ERROR while loading design

A similar issue is observed when Condensed I/O is chosen as the Port I/O Style.

The error message only occurs when the 'HELLO Format' option is de-selected in the core configuration GUI.


This is a known issue which is due to be fixed in a future release of the core.

Currently, example design simulation without the "HELLO format" option is not supported.

The error only occurs with some third party simulators, for example Questa, but not with Vivado XSIM. To work around it, you can run post-synthesis simulation in Questa.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

08/10/2014 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54648 LogiCORE IP Serial RapidIO Gen2 Core - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 62375
日期 02/15/2021
状态 Active
Type 已知问题
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