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For Kintex-7 and Virtex-7 designs cpll_pd_i should be driven by cpllpd_ovrd_i.
If the Transceiver files have been updated (due to line rate change) no action is required.
If the design is using all of the default files generated by the Xilinx JESD204 IP the following solutions are available:
AR# 62470 | |
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日期 | 10/14/2014 |
状态 | Active |
Type | 综合文章 |
IP |