AR# 62470

描述

解决方案

For Kintex-7 and Virtex-7 designs cpll_pd_i should be driven by cpllpd_ovrd_i.  

If the Transceiver files have been updated (due to line rate change) no action is required.  

If the design is using all of the default files generated by the Xilinx JESD204 IP the following solutions are available:

• Update the design to Vivado 2014.3 and use JESD204 v6.0 where this issue has been fixed.
   
• If JESD204 has been generated with 'Support Logic in Example Design', regenerate the GT Wizard with the required line rate and replace the files by following the procedure found in JESD204 PG066 page 77 'Updating the Transceiver Configuration'.
   
• If the JESD204 IP has been generated with 'Shared Logic in Core', regenerate the JESD204 Core and ensure that the DCP in the 'Out of Context Settings' is disabled. 
  Next, open the <corename>_gtwizard_0_gt.v file in any text editor other than the Vivado default and change the following line:
   
                      cpll_pd_i = cpllreset_ovrd_i;          
  to
                      cpll_pd_i = cpllpd_ovrd_i;