AR# 62483

MIG UltraScale 设计咨询(所有存储器类型)— VRP 引脚及 DCI 级联要求

描述

该设计咨询涵盖 MIG UltraScale 内核。

没有使用 DCI 级联时,所有包含存储器接口引脚的 I/O bank 都需要连接 VRP 引脚。

这包括仅输出 bank,例如用于仅地址/控制引脚的 bank。

运行速率超过 2133Mbps 的接口不支持 DCI 级联。

这会影响由 MIG UltraScale 生成的所有存储器接口类型。

解决方案

不使用 DCI 级联的设计:


所有 I/O bank(包括只支持输出的 bank)都需要连接一个 VRP 引脚,因为所有 I/O(“reset_n”除外)都采用 DCI I/O 标准,因而需要 VRP。

在 2014.4 版本中为输出添加了 DCI 标准(例如 SSTL*_DCI),从而使用受控的输出阻抗。

以前输出端使用未校正的输出阻抗选项(而非受控 DCI 版本),需要参考 VRP 引脚上的外部参考电阻来进行校正。

受控输出阻抗增加了校正程序,以补偿温度、工艺或电压变化。

必须遵守UltraScale 架构 FPGA SelectIO 资源用户指南 (UG571) 中的所有 DCI 规则。

http://china.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf


唯一不遵循这一要求的是 reset_n 引脚,因为其不使用 DCI I/O 标准。 

如果将 reset_n 放在非存储器接口 bank 中,就不需要 VRP。

如需更多信息,敬请参考 UltraScale 架构 FPGA 内存 IP 产品指南 (PG150)。

http://china.xilinx.com/support/documentation/ip_documentation/mig/v1_0/pg150-ultrascale-memory-ip.pdf

使用 DCI 级联的设计:


DCI cascading can be supported for interfaces running at and below 2133Mbps.

(PG150) 及存储器接口向导都将进行更新支持Vivado 2016.1 版本,以便包含 DCI 级联支持指南。

必须遵守UltraScale 架构 FPGA SelectIO 资源用户指南 (UG571) 中的所有 DCI 规则。

http://china.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf


修订历史:

2015 年 10 月 30 日 — 经过更新,支持 2133Mbps 和以下 DCI 级联

10/20/14——初始版本

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
N/A N/A
69978 Zynq UltraScale+ MPSoC: How to enable UHS (SD 3.0) support for ZCU102 and ZCU106 evaluation board PetaLinux BSPs N/A N/A
69970 2017.3 Zynq UltraScale+ MPSoC: XSDB using SmartLynq Data Cable does not show the MicroBlaze PMU MDM. N/A N/A
69975 2017.1-2017.4 PetaLinux: QEMU flash_stripe.c is not included in the QEMU utilities shipped with PetaLinux N/A N/A
69979 2017.3 PetaLinux: Change to the name of the FIT image (image.ub) in the petalinux-config menu not reflected once images are built N/A N/A
69977 XAPP1241 - What is the convergence time for PICXO? N/A N/A
69436 UltraScale/UltraScale+ LPDDR3 IP - Mode Register Settings N/A N/A
69433 2017.1/2 Zynq UltraScale+ MPSoC: Linux kernel crash from EDAC driver N/A N/A
69438 UltraScale/UltraScale+ RLDRAM3 IP v1.4 - Vivado 2016.4 and 2017.x - Previously working interface now fails calibration at Write DQ/DM Deskew step N/A N/A
69430 UltraScale/UltraScale+ - Are the IS_D_INVERTED attributes supported for the IFD/OFD/ODDR primitives N/A N/A
69431 2017.2 LogiCORE IP MIPI CSI-2 Receiver Subsystem v2.2 (Rev.2) - Patch Updates for the LogiCORE IP MIPI CSI-2 Receiver Subsystem v2.2 (Rev.2) N/A N/A
69435 UltraScale/UltraScale+ LPDDR3 IP - PCBA Layout Guidelines N/A N/A
N/A N/A
69605 SDx 2017.2 - Cannot import projects created in the 2016.2 version in SDx 2017.2 N/A N/A
69606 2017.2 SDx - Cannot connect the TCF agent running on Linux N/A N/A
69603 ISE S6 VM - SDK breakpoint debug feature does not work if a Digilent USB cable is used to program the board N/A N/A
69609 2017.2 SDx - XSIM instance does not exit after SDSoC emulation is closed N/A N/A
69607 SDK 2017.2 - System Debugger does not have access to PL address regions on Zynq UltraScale+ MPSoC N/A N/A
69600 2017.1/2 Zynq UltraScale+ MPSoC: Yocto MALI libraries with FBdev work-around for Zynq UltraScale+ ES1 Silicon N/A N/A
N/A N/A
69701 Zynq UltraScale+ RFSoC: RF Data Converter IP Change Log N/A N/A
N/A N/A
69844 Virtex UltraScale+ FPGA VCU1525 Data Center Acceleration Development Board - Known Issues and Release Notes Master Answer Record N/A N/A
69848 XDC macro is unable to place FIFO cells in adjacent BRAM sites N/A N/A
69845 Vivado IP Integrator - CRITICAL WARNING: [BD 41-1756] The number of cascaded segments <##>. accessed through interconnect interface exceeds the limit of 16. N/A N/A
69846 2017.x Vivado - The hierarchy source view in Vivado 2017.x is incorrect or takes a long time to update compared with Vivado 2016.x N/A N/A
N/A N/A
69570 XPE - 7 Series - When running the boundary scan instructions such as SAMPLE or EXTEXT, higher power can be seen on the GT rails (MGTAVcc & MGTAVtt) when compared to the estimated GT power rails N/A N/A
69576 2017.2 Zynq UltraScale+ MPSoC: Linux UBIFS support for QSPI (Only in I/O mode) N/A N/A
69573 UltraScale/UltraScale+ DDR4 IP - 2017.x multi-controller designs fail calibration at WRITE_DQS_TO_DQ (complex) - IBUF_LOW_PWR attribute (2016.4 upgrade) N/A N/A
69579 XPE - When importing a .xpe file from Vivado corruption is seen in the cells of the spreadsheet. N/A N/A
69577 2017.1 Licensing - SDNet 2017.1 - ERROR: SDNet cannot obtain license N/A N/A
N/A N/A
69672 High Speed SelectIO Wizard - Receive interfaces should not use edge aligned and set a non zero delay_value. N/A N/A
69670 Zynq UltraScale+ MPSoC - What is the behavior of the PS I/Os pre-configuration N/A N/A
69676 DMA Subsystem for PCI Express (Vivado 2017.2) - MSI-X Interrupt can hang in a specific scenario N/A N/A
69671 LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - When using 7 Series Devices to implement MIPI D-PHY TX, why do we see overshoot on the output signal during HS-->LP transmission? N/A N/A
69674 Export ILA captured data in Binary, decimal, or ASCII format N/A N/A
N/A N/A
69332 2017.1 Zynq UltraScale+ MPSoC:U-boot 需要一个补丁在 HS200 下运行 eMMC N/A N/A
69333 7 Series XADC - How many conversions does it take for the channel to update after a change N/A N/A
N/A N/A
69951 How to update the SmartLynq cable firmware from 2017.2 to 2017.3 using Vivado? N/A N/A
69952 PetaLinux 2017.3 - Product Update Release Notes and Known Issues N/A N/A
69955 SmartLynq cable speed degradation N/A N/A
69956 2017.3 Vivado Timing - Add flight-time delay data for XAZU4 and XAZU5 devices N/A N/A
6995 4.1i Foundation - A Timing Simulation netlist is always created on subsequent runs, regardless of whether or not the Simulation Netlist switch is set to "OFF" N/A N/A
69173 2017.1 LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - Patch Updates for the LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) N/A N/A
69179 Vivado 2017.1 [BRAM inference] - How to achieve better block RAM utilization from Vivado synthesis when using asymmetric port widths - Inferred RAM and XPM (Simple Dual Port) N/A N/A
69177 Vivado 2017.1 — 版本 'GLIBC_2.9' 带来的发行问题尚未发现 N/A N/A
N/A N/A
69271 HDMI Receiver (RX) Subsystem v2.0 (Rev. 4) - Why does the HDMI RX Subsystem continue to try to decrypt the video even when the HDMI source has turned off encryption? N/A N/A
69276 Zynq UltraScale+ MPSoC - PS SPI routed through EMIO, read data is always 0 N/A N/A
69274 LogiCORE IP MIPI D-PHY v3.1, v3.1 (Rev. 1) and v4.0 (Rev. 1) - Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY RX? N/A N/A
69275 DMA Subsystem for PCI Express (Vivado 2017.1) - Support for x8gen3 in -2LV UltraScale devices N/A N/A
69272 2017.3 Zynq UltraScale+ MPSoC - DBG_TRACE clock attribute must match pl_ps_trace_clk frequency N/A N/A
N/A N/A
699 6.0: Programmable Key: Change parallel port settings if key is not seen. N/A N/A
69441 MIPI CSI-2 Receiver Subsystem v2.2 (Rev.2) - Why is the MIPI CSI-2 Receiver with Clock/Data skew calibration set to Auto/Fixed, failing during implementation? N/A N/A
69447 Zynq UltraScale+ MPSoC - PS SMMU cannot distinguish between multiple masters connected to a single PS port through SmartConnect N/A N/A
69446 Zynq UltraScale+ MPSoC Example Design - Use AXI HPC port to perform coherent transfers N/A N/A
69443 2017.1 Vivado IP 流程 — 在 AXI PCIE3 IP 核上运行 OOC 综合时,Kintex UltraScale 设计发生了程序异常终止情况。 N/A N/A
69444 2017.2 DMA Subsystem for PCI Express - Support for x8gen3 in -2LV UltraScale devices N/A N/A
69449 Virtex UltraScale+ FPGA VCU118 Evaluation Kit - U41 is connected to VCC1V2 N/A N/A
N/A N/A
6971 Virtex - Virtex devices have the potential for high current draw for the engineering samples N/A N/A
69814 The SmartLynq Cable GPIO 8-Bit Interface supports 3.3 volts only N/A N/A
69815 Virtex UltraScale+ FPGA VCU118 Evaluation Kit - Reprogramming the Maxim Integrated Power Controllers N/A N/A
69811 Xilinx UltraScale+ 开发板与套件 - Maxim 集成功耗解决方案 N/A N/A
69816 XPE - Zynq UltraScale Plus - What is the power consumption of the Processor Subsystem (PS) when the part is powered and unconfigured N/A N/A
69812 2016.4-2017.2 PetaLinux: Build failed due to "error "timeout while establishing a connection with SDK"' N/A N/A
6981 CPLD XC9500/XL/XV - Which JTAG pins have internal pull-up resistors? Do any of the JTAG pins need external pull-up resistors? N/A N/A
69685 Zynq UltraScale+ MPSoC, PMUFW - PS AXI interconnect performance degradation in Vivado 2017.1 N/A N/A
69683 LogiCORE DisplayPort TX Subsystem v2.0 (Rev. 2) - Why is there sometimes unexpected data skew between lanes when enabling the PRBS-7 option? N/A N/A
69688 2017.2 Zynq UltraScale+ MPSoC: FSBL – SD boot fails with data abort exception when a53_64 targeted application is running at upper PS DDR or PL DDR memory N/A N/A
6968 10.1 Floorplanner - "ERROR:Pack:679 - Unable to obey design constraints." (No DRC check on Virtex FF clock) N/A N/A
69782 2017.2 SDx - Excessive System compile time on Windows N/A N/A
69780 2016.4-2017.4 Zynq UltraScale+ MPSoC: PetaLinux does not correctly override the U-boot environment variables to set SD boot when both eMMC(SDIO0) and SD(SDIO1) are enabled in design N/A N/A
69789 UltraScale/UltraScale+ - How to change the pinouts for XAPP1274 Native Mode N/A N/A
69781 LogiCORE IP LTE Uplink Channel Decoder v4.0 - Unexpected simulation results in VCS or Vivado Simulator when Balanced optimization is selected in conjunction with 1 Turbo decoder PU. N/A N/A
69787 LogiCORE IP Color Filter Array Interpolation (CFA) v7.0 - Why is the DEBUG feature not enabled when I select the Debug Checkbox? N/A N/A
N/A N/A
69048 2017.x Vivado Simulation - Known Issues N/A N/A
69044 Dual-purpose I2C pins used as output ports do not have correct signal output N/A N/A
69041 UltraScale/UltraScale+ LPDDR3 IP - 大范围 I/O 分组中允许的 LPDDR3 非支持性频率(超过 533MHz) N/A N/A
69047 2017.1 Install - I am unable to download Vivado Design Suite 2017.1 N/A N/A
69141 UltraScale/UltraScale+ LPDDR3 IP - Memory Model Simulation Errors for QuestaSim and Other Simulators N/A N/A
69140 Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit - ARM 20-pin JTAG connector wires N/A N/A
69149 2016.4 Zynq UltraScale+ MPSoC: FSBL fails to decrypt bitstream if the image is place in QSPI at a multiple of 32K offset N/A N/A
N/A N/A
69209 2017.1 - IP Encryption - Watermark in the public key for encryption N/A N/A
69202 Kintex UltraScale FPGA 及 Virtex UltraScale FPGA 的设计咨询 — 3D IC 器件在加电及断电过程中可能会在位于从 SLR 的 I/O 上启用弱上拉 N/A N/A
69206 2017.1 - IBERT - RXOUTCLK frequency gets doubled when using IN-System IBERT core N/A N/A
N/A N/A
69308 UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2017.1) — GT DRP 仲裁器模块 N/A N/A
6930 Packaging FPGA/CPLD/PROM - I want to bake half the number of devices in the vacuum bag. What does Xilinx recommend for this? How do I use the Humidity Indicator Card? N/A N/A
69920 I need to bring CPLLREFCLKSEL to the top of the hierarchy to be able to make speed changes N/A N/A
69928 2017.3 Zynq UltraScale+ MPSoC: Low Performance during Flash (QSPI and NAND) Programming N/A N/A
69921 7 Series GTX IBIS-AMI - Linux *_gtx_ami_rx.ibs model has duplicated lines N/A N/A
69929 2017.3 Vivado - The Message console does not allow filtering of the displayed messages by severity N/A N/A
AR# 62483
日期 01/18/2016
状态 Active
Type 设计咨询
器件
IP