AR# 6250

3.1i COREGen - Required order of analysis/compilation for CORE Generator VHDL and Verilog behavioral model libraries

描述

c_ip2, c_ip3, c_ip4, c_ip5

Urgency: Hot

General Description:

There is a definite hierarchical relationship between the VHDL behavioral models

delivered by COREGen. This must be considered in order to compile them without

error in preparation, prior to simulation. For VHDL, the hierarchy must be compiled

from the bottom up (i.e., "primitive" models must be compiled or analyzed before

the "macro" models in which they are instantiated).

For Verilog, the compilation order is not critical, but using the recommended

compile order will minimize the number of warnings issued during the compile

process.

解决方案

2.1i VHDL:

The required order for the models shipped in the C_IP2 release is:

prims_constants*.vhd

prims_comps*.vhd

prims_utils*.vhd

prims_sim_arch*.vhd

ul_utils.vhd

*pack.vhd

c_*comp.vhd

c_reg*.vhd

c_*.vhd

*.vhd

The last item in the list will cause some models to be recompiled, but

this is not a problem -- no errors will be issued by ModelSIM regarding

recompiled models. The only requirement is that any lower level models

need to be compiled before the higher level models.

The required order shown above may change slightly with each IP update

that Xilinx ships, but updated information on compile order requirements

will be included with each update, along with this solution record.

2.1i, C_IP3:

The required order for the VHDL models shipped in the C_IP3 release is:

prims_constants*.vhd

prims_comps*.vhd

prims_utils*.vhd

prims_sim_arch*.vhd

ul_utils.vhd

*pack.vhd

c_*comp.vhd

c_reg*.vhd

c_addsub_v1_0.vhd

c_mux_bus_v1_0.vhd

c_*.vhd

*.vhd

The recommended order for compiling the XilinxCoreLib Verilog libraries in C_IP3 is:

C_REG_FD_V1_0.v

C_ADDSUB*.v

*.v

2.1i, C_IP4:

For the C_IP4 release, you must make sure that the VHDL UNISIM library is compiled

first, before the VHDL XilinxCoreLib library.

The UNISIM library is located in $XILINX/vhdl/src. You will need to compile

the following files:

unisim_VPKG.vhd

unisim_VCOMP.vhd

unisim_VITAL.vhd

unisim_VCFG4K.vhd

Sample commands for compiling the UNISIM library for ModelSIM are as follows:

vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd

vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd

vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd

vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd

----------------------------------------------

XILINXCORELIB Compilation

----------------------------------------------

When compiling the XilinxCoreLib library, the required order for the VHDL models

shipped in the C_IP4 release is:

(NOTE: Be sure to include the "*" symbol.)

prims_constants*.vhd

prims_comps*.vhd

prims_utils*.vhd

prims_sim_arch*.vhd

ul_utils.vhd

*pack.vhd

c_*comp.vhd

c_reg*.vhd

c_addsub*.vhd

c_mux_bus*..vhd

c_*.vhd

vfft_utils.vhd

*.vhd

If your simulator requires you to compile each model separately or does not

allow you to recompile the same model more than once, you can use this

order:

prims_constants_v1_0.vhd

prims_constants.vhd

prims_comps_v1_0.vhd

prims_comps.vhd

prims_utils.vhd

prims_utils_v1_0.vhd

prims_sim_arch.vhd

prims_sim_arch_v1_0.vhd

ul_utils.vhd

vfft_utils.vhd

vfft1024.vhd

vfft1024_comp.vhd

vfft16.vhd

vfft16_comp.vhd

vfft256.vhd

vfft256_comp.vhd

vfft64.vhd

vfft64_comp.vhd

mulVHT.vhd

mulVHT_comp.vhd

acc2sVHT.vhd

acc2sVHT_comp.vhd

addsVHT.vhd

addsVHT_comp.vhd

adreVHT.vhd

adreVHT_comp.vhd

adrleVHT.vhd

adrleVHT_comp.vhd

cmpsVHT.vhd

cmpsVHT_comp.vhd

mux2VHT.vhd

mux2VHT_comp.vhd

mux3VHT.vhd

mux3VHT_comp.vhd

mux4VHT.vhd

mux4VHT_comp.vhd

pscVHT.vhd

pscVHT_comp.vhd

regceVHT.vhd

regceVHT_comp.vhd

saddceVHT.vhd

saddceVHT_comp.vhd

subreVHT.vhd

subreVHT_comp.vhd

subrleVHT.vhd

subrleVHT_comp.vhd

tsb16sVHT.vhd

tsb16sVHT_comp.vhd

tsb16xVHT.vhd

tsb16xVHT_comp.vhd

tsb32xVHT.vhd

tsb32xVHT_comp.vhd

sqrootVHT.vhd

sqrootVHT_comp.vhd

trigtabl_v1_0.vhd

trigtabl_v1_0_comp.vhd

dividervht.vhd

dividervht_comp.vhd

sdafirVHT.vhd

sdafirVHT_comp.vhd

pdafirVHT.vhd

pdafirVHT_comp.vhd

nco_v1_0.vhd

ncoiq_v1_0.vhd

c_reg_fd_v1_0.vhd

c_reg_fd_v1_0_comp.vhd

mult_vgen_v1_0.vhd

mult_vgen_v1_0_comp.vhd

dpramVHT.vhd

dpramVHT_comp.vhd

romrVHT.vhd

romrVHT_comp.vhd

syncramVHT.vhd

syncramVHT_comp.vhd

kdcm_v1_0.vhd

kdcm_v1_0_comp.vhd

kcmVHT.vhd

kcmVHT_comp.vhd

kcmpipeVHT.vhd

kcmpipeVHT_comp.vhd

integVHT.vhd

integVHT_comp.vhd

m12x12.vhd

m12x12_comp.vhd

m8x8.vhd

m8x8_comp.vhd

fifosyncVHT.vhd

fifosyncVHT_comp.vhd

delayVHT.vhd

delayVHT_comp.vhd

combfiltVHT.vhd

combfiltVHT_comp.vhd

mem_init_file_pack.vhd

c_mem_dp_block_v1_0.vhd

c_mem_sp_block_v1_0_comp.vhd

c_mem_sp_block_v1_0.vhd

c_addsub_v1_0.vhd

c_addsub_v1_0_comp.vhd

c_accum_v1_0.vhd

c_accum_v1_0_comp.vhd

c_compare_v1_0.vhd

c_compare_v1_0_comp.vhd

c_mux_bus_v1_0.vhd

c_mux_bus_v1_0_comp.vhd

c_counter_binary_v1_0.vhd

c_decode_binary_v1_0_comp.vhd

c_decode_binary_v1_0.vhd

c_gate_bit_bus_v1_0_comp.vhd

c_dist_mem_v1_0.vhd

c_gate_bit_bus_v1_0.vhd

c_mux_slice_bufe_v1_0_comp.vhd

c_gate_bit_v1_0.vhd

c_gate_bus_v1_0.vhd

c_mux_bit_v1_0.vhd

c_mux_slice_bufe_v1_0.vhd

c_mux_slice_buft_v1_0_comp.vhd

c_mux_slice_buft_v1_0.vhd

c_reg_ld_v1_0.vhd

c_reg_ld_v1_0_comp.vhd

c_mux_bit_v1_0_comp.vhd

c_shift_fd_v1_0.vhd

c_shift_fd_v1_0_comp.vhd

c_shift_ram_v1_0.vhd

c_shift_ram_v1_0_comp.vhd

c_twos_comp_v1_0.vhd

c_twos_comp_v1_0_comp.vhd

pipeline.vhd

c_dist_mem_v1_0_comp.vhd

c_mem_dp_block_v1_0_comp.vhd

c_counter_binary_v1_0_comp.vhd

c_gate_bus_v1_0_comp.vhd

c_gate_bit_v1_0_comp.vhd

async_fifo_pkg.vhd

async_fifo_v1_0.vhd

async_fifo_v1_0_comp.vhd

The recommended order for compiling the XilinxCoreLib Verilog libraries in C_IP4 is:

C_REG_FD_V1_0.v

C_ADDSUB*.v

*.v

If your simulator requires you to compile the models individually, you may use this

order:

C_ACCUM_V1_0.v

C_ADDSUB_V1_0.v

C_COMPARE_V1_0.v

C_COUNTER_BINARY_V1_0.v

C_DA_FIR_V2_0.v

C_DECODE_BINARY_V1_0.v

C_DIST_MEM_V1_0.v

C_GATE_BIT_BUS_V1_0.v

C_GATE_BIT_V1_0.v

C_GATE_BUS_V1_0.v

C_MEM_DP_BLOCK_V1_0.v

C_MEM_SP_BLOCK_V1_0.v

C_MUX_BIT_V1_0.v

C_MUX_BUS_V1_0.v

C_MUX_SLICE_BUFE_V1_0.v

C_MUX_SLICE_BUFT_V1_0.v

C_REG_FD_V1_0.v

C_REG_LD_V1_0.v

C_SHIFT_FD_V1_0.v

C_SHIFT_RAM_V1_0.v

C_TWOS_COMP_V1_0.v

DIVIDERVHT.v

MULT_VGEN_V1_0.v

PIPELINE.v

acc2sVHT.v

addsVHT.v

adreVHT.v

adrleVHT.v

async_fifo_v1_0.v

cmpsVHT.v

combfiltVHT.v

da_fir_v1_0.v

delayVHT.v

dpramVHT.v

fifosyncVHT.v

integVHT.v

kcmVHT.v

kcmpipeVHT.v

kdcm_v1_0.v

mulVHT.v

mux2VHT.v

mux3VHT.v

mux4VHT.v

nco_v1_0.v

ncoiq_v1_0.v

ncoiqvht.v

ncovht.v

pdafirVHT.v

pscVHT.v

regceVHT.v

romrVHT.v

saddceVHT.v

sdafirVHT.v

sincos_v2_0.v

sqrootVHT.v

subreVHT.v

subrleVHT.v

syncramVHT.v

trigtablVHT.v

trigtabl_v1_0.v

tsb16sVHT.v

tsb16xVHT.v

tsb32xVHT.v

2.1i, C_IP5:

For the C_IP5 release, you must make sure that the VHDL UNISIM library is compiled

first, before the VHDL XilinxCoreLib library. (Note: The C_IP5 IP release is only

compatible with the 2.1i release of the Xilinx software.)

The UNISIM library is located in $XILINX/vhdl/src. You will need to compile

the following files:

unisim_VPKG.vhd

unisim_VCOMP.vhd

Sample commands for compiling the UNISIM library for ModelSIM are as follows:

vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd

vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd

vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd

vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd

----------------------------------------------

XILINXCORELIB Compilation

----------------------------------------------

When compiling the XilinxCoreLib library, the required order for the VHDL models

shipped in the C_IP5 release is:

(NOTE: Be sure to include the "*" symbol.)

prims_constants*.vhd

prims_comps*.vhd

prims_utils*.vhd

prims_sim_arch*.vhd

ul_utils.vhd

*pack.vhd

c_*comp.vhd

c_reg*.vhd

c_addsub*.vhd

c_mux_bus*..vhd

c_*.vhd

vfft_utils.vhd

v*_comp.vhd

*.vhd

If your simulator requires you to compile each model separately or does not

allow you to recompile the same model more than once, you can use this

order:

ul_utils.vhd

nco_v1_0.vhd

ncoiq_v1_0.vhd

vfft_utils.vhd

vfft1024_comp.vhd

vfft1024.vhd

vfft16_comp.vhd

vfft16.vhd

vfft256_comp.vhd

vfft256.vhd

vfft64_comp.vhd

vfft64.vhd

trigtabl_v1_0.vhd

trigtabl_v1_0_comp.vhd

dafir_pack.vhd

da_fir_v1_0.vhd

da_fir_v1_0_comp.vhd

da_fir_v2_0.vhd

da_fir_v2_0_comp.vhd

prims_constants_v1_0.vhd

mem_init_file_pack.vhd

prims_utils_v1_0.vhd

c_reg_fd_v1_0.vhd

c_reg_fd_v1_0_comp.vhd

c_dist_mem_v1_0.vhd

c_dist_mem_v1_0_comp.vhd

c_mem_dp_block_v1_0.vhd

c_mem_dp_block_v1_0_comp.vhd

c_addsub_v1_0.vhd

c_addsub_v1_0_comp.vhd

c_compare_v1_0.vhd

c_compare_v1_0_comp.vhd

c_mux_bus_v1_0.vhd

c_mux_bus_v1_0_comp.vhd

c_counter_binary_v1_0.vhd

c_counter_binary_v1_0_comp.vhd

c_gate_bus_v1_0.vhd

c_gate_bus_v1_0_comp.vhd

c_gate_bit_v1_0.vhd

c_gate_bit_v1_0_comp.vhd

prims_comps_v1_0.vhd

async_fifo_pkg.vhd

async_fifo_v1_0.vhd

async_fifo_v1_0_comp.vhd

mult_vgen_v1_0.vhd

mult_vgen_v1_0_comp.vhd

c_mem_sp_block_v1_0.vhd

c_mem_sp_block_v1_0_comp.vhd

kdcm_v1_0.vhd

kdcm_v1_0_comp.vhd

dividervht.vhd

dividervht_comp.vhd

m12x12.vhd

m12x12_comp.vhd

m8x8.vhd

m8x8_comp.vhd

sdafirVHT.vhd

sdafirVHT_comp.vhd

fifosyncVHT.vhd

fifosyncVHT_comp.vhd

dpramVHT.vhd

dpramVHT_comp.vhd

romrVHT.vhd

romrVHT_comp.vhd

syncramVHT.vhd

syncramVHT_comp.vhd

sqrootVHT.vhd

sqrootVHT_comp.vhd

mulVHT.vhd

mulVHT_comp.vhd

kcmVHT.vhd

kcmVHT_comp.vhd

kcmpipeVHT.vhd

kcmpipeVHT_comp.vhd

integVHT.vhd

integVHT_comp.vhd

pdafirVHT.vhd

pdafirVHT_comp.vhd

delayVHT.vhd

delayVHT_comp.vhd

combfiltVHT.vhd

combfiltVHT_comp.vhd

acc2sVHT.vhd

acc2sVHT_comp.vhd

addsVHT.vhd

addsVHT_comp.vhd

adreVHT.vhd

adreVHT_comp.vhd

adrleVHT.vhd

adrleVHT_comp.vhd

cmpsVHT.vhd

cmpsVHT_comp.vhd

mux2VHT.vhd

mux2VHT_comp.vhd

mux3VHT.vhd

mux3VHT_comp.vhd

mux4VHT.vhd

mux4VHT_comp.vhd

pscVHT.vhd

pscVHT_comp.vhd

regceVHT.vhd

regceVHT_comp.vhd

saddceVHT.vhd

saddceVHT_comp.vhd

subreVHT.vhd

subreVHT_comp.vhd

subrleVHT.vhd

subrleVHT_comp.vhd

tsb16sVHT.vhd

tsb16sVHT_comp.vhd

tsb16xVHT.vhd

tsb16xVHT_comp.vhd

tsb32xVHT.vhd

tsb32xVHT_comp.vhd

c_accum_v1_0.vhd

c_accum_v1_0_comp.vhd

c_decode_binary_v1_0.vhd

c_decode_binary_v1_0_comp.vhd

c_gate_bit_bus_v1_0.vhd

c_gate_bit_bus_v1_0_comp.vhd

c_mux_slice_bufe_v1_0.vhd

c_mux_slice_bufe_v1_0_comp.vhd

c_mux_slice_buft_v1_0.vhd

c_mux_slice_buft_v1_0_comp.vhd

c_reg_ld_v1_0.vhd

c_reg_ld_v1_0_comp.vhd

c_mux_bit_v1_0.vhd

c_mux_bit_v1_0_comp.vhd

c_shift_fd_v1_0.vhd

c_shift_fd_v1_0_comp.vhd

c_shift_ram_v1_0.vhd

c_shift_ram_v1_0_comp.vhd

c_twos_comp_v1_0.vhd

c_twos_comp_v1_0_comp.vhd

pipeline.vhd

prims_constants.vhd

prims_comps.vhd

prims_utils.vhd

prims_sim_arch.vhd

prims_sim_arch_v1_0.vhd

The recommended order for compiling the XilinxCoreLib Verilog libraries in C_IP5 is:

C_REG_FD_V1_0.v

C_ADDSUB*.v

*.v

If your simulator requires you to compile the models individually, you may use this

order:

C_REG_FD_V1_0.v

C_ADDSUB_V1_0.v

C_ACCUM_V1_0.v

C_COMPARE_V1_0.v

C_COUNTER_BINARY_V1_0.v

C_DA_FIR_V2_0.v

C_DECODE_BINARY_V1_0.v

C_DIST_MEM_V1_0.v

C_GATE_BIT_BUS_V1_0.v

C_GATE_BIT_V1_0.v

C_GATE_BUS_V1_0.v

C_MEM_DP_BLOCK_V1_0.v

C_MEM_SP_BLOCK_V1_0.v

C_MUX_BIT_V1_0.v

C_MUX_BUS_V1_0.v

C_MUX_SLICE_BUFE_V1_0.v

C_MUX_SLICE_BUFT_V1_0.v

C_REG_LD_V1_0.v

C_SHIFT_FD_V1_0.v

C_SHIFT_RAM_V1_0.v

C_TWOS_COMP_V1_0.v

DIVIDERVHT.v

MULT_VGEN_V1_0.v

PIPELINE.v

acc2sVHT.v

addsVHT.v

adreVHT.v

adrleVHT.v

async_fifo_v1_0.v

cmpsVHT.v

combfiltVHT.v

da_fir_v1_0.v

delayVHT.v

dpramVHT.v

fifosyncVHT.v

integVHT.v

kcmVHT.v

kcmpipeVHT.v

kdcm_v1_0.v

mulVHT.v

mux2VHT.v

mux3VHT.v

mux4VHT.v

nco_v1_0.v

ncoiq_v1_0.v

ncoiqvht.v

ncovht.v

pdafirVHT.v

pscVHT.v

regceVHT.v

romrVHT.v

saddceVHT.v

sdafirVHT.v

sincos_v1_0.v

sqrootVHT.v

subreVHT.v

subrleVHT.v

syncramVHT.v

trigtablVHT.v

trigtabl_v1_0.v

tsb16sVHT.v

tsb16xVHT.v

tsb32xVHT.v

3.1i VHDL:

Please refer to the vhdl_analyze_order file in

$XILINX/vhdl/src/XilinxCoreLib for the required

VHDL model analyze order.

3.1i Verilog:

Please refer to the verilog_analyze_order file in

$XILINX/verilog/src/XilinxCoreLib for information on the

recommended compile order.

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AR# 6250
日期	10/12/2011
状态	Archive
Type	综合文章

AR# 6250

3.1i COREGen - Required order of analysis/compilation for CORE Generator VHDL and Verilog behavioral model libraries

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AR# 6250

3.1i COREGen - Required order of analysis/compilation for CORE Generator VHDL and Verilog behavioral model libraries

描述

解决方案