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AR# 62593

UltraScale RLDRAM3 - default bank selection for 72-bit designs fails to select all data byte lanes

描述

Version Found: RLDRAM3 v6.0

Version Resolved: See (Xilinx Answer 69037)

The default bank and byte selection for a MIG UltraScale RLDRAM3 72-bit design fails to select all data byte lanes which prevents the IP core from being generated.

解决方案

To work around this issue, the remaining data byte lanes must be manually assigned to a bank and byte lane before the IP core can be successfully generated.

Revision History:

10/23/2014 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69037 UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues N/A N/A
AR# 62593
日期 12/19/2017
状态 Active
Type 已知问题
器件
Tools
IP
的页面