The following answer records cover current known issues as well as commonly asked questions related to MIG UltraScale.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).
The Xilinx MIG Solution Center is available to address all
questions related to Memory Interfaces.
Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
MIG Known Issues
(Xilinx Answer 58435) MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions
MIG Design Advisories
(Xilinx Answer 33566) Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
MIG UltraScale Frequently Asked Questions
(Xilinx Answer 59625) MIG UltraScale - Design Methodology Checklist Article
MIG I/O Pin Planning Steps - (UG899) > I/O Pin Planning for UltraScale Memory IP
MIG Clocking Guidelines- (PG150) > Memory Interface Type > Designing with the Core > Clocking
Memory Interface PCB Guidelines - (UG583)
Memory Interface Pin Rules - (PG150) > Memory Interface Type > Designing with the Core > Pin and Bank Rules
Multiple Memory Interface IP Usage - (PG150) > Multiple IP Cores
Upgrading MIG IP to 2015.1 - (PG150) > Appendices > Migrating and Upgrading
Pre-2015.1 Frequently Asked Questions
(Xilinx Answer 62442) MIG UltraScale - Is there an automated way to create MIG IP with a custom pin-out until MIG pin planning is integrated into IO Pin Planner in 2015.1?
(Xilinx Answer 61075) MIG UltraScale - What is the recommended flow for creating multiple MIG interfaces within a single design?
(Xilinx Answer 61304) MIG UltraScale - Clocking Guidelines and Requirements Article