AR# 62930


UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations


Version Found: DDR4 v6.1, DDR3 v6.1

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

tCCD (including tCCD_L and tCCD_S) and tRTW violations can occur as a result of a known issue with the MIG UltraScale DDR3/DDR4 controller for DDR4 x16 and DDR3/DDR4 multi-rank configurations only.

All other single rank or DDR4 x4 and x8 configurations or x16 interfaces running <1333Mbps are not affected.

These violations can be seen in behavioral simulations and can result in data errors in hardware and should not be ignored.


In order to resolve this issue installing the attached tactical IP patch is required.

To install the patch, extract the contents of "" to the 2014.4 install directory (for example, C:\Xilinx\Vivado\2014.4\), then open Vivado 2014.4 and regenerate all of your MIG UltraScale IP.

Note: This tactical patch is only compatible with the Vivado 2014.4 and MIG UltraScale v6.1 IP.

Revision History:

12/16/2014 - Initial Release


文件名 文件大小 File Type 1 MB ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 62930
日期 01/11/2018
状态 Active
Type 已知问题
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