AR# 63122


MIG 7 Series DDR2/DDR3 v2.3 - Automated and manual write window margin check feature is not available on the example design


Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)

In MIG v2.3 available with Vivado 2014.4, automated or manual write window margin cannot be found with the example design.

Why is this occurring?


Due to calibration algorithm update since MIG v2.3, MMCM phase shift is used for OCLKDELAY calibration.

See (Xilinx Answer 62368) For more details about the calibration update.

Before MIG v2.3, the write window checker of the example design uses PHASER_OUT stage3 tap adjustment to find the edge or window.

It is not available on the MIG v2.3 example design. 

Revision History:
01/20/2014: Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 63122
日期 01/23/2015
状态 Active
Type 已知问题
器件 More Less
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