AR# 63238

UltraScale RLDRAM3 - Tactical Patch - timing failures in mmcm_clkout0 domain


Version Found:RLDRAM3 v6.1

Version Resolved: See (Xilinx Answer 69037)

The following path (or similar paths) may fail timing for MIG UltraScale RLDRAM3 designs as a result of a long route delays or as a result of incorrect speed files used for -1 and -1L devices:

Slack (VIOLATED) :        -0.202ns  (required time - arrival time)
  Source:                 rldram3_example_top_ab/u_rldram3_ctrl_AB/inst/u_rld3_mem_intfc/u_rld_ui/usr_addr_fifo/u_af/RDCLK
                            (rising edge-triggered cell FIFO36E2 clocked by mmcm_clkout0_1  {rise@0.000ns fall@1.876ns period=3.752ns})
  Destination:            rldram3_example_top_ab/u_rldram3_ctrl_AB/inst/u_rld3_mem_intfc/u_rld_ui/usr_wr_fifo/gen_wdf0[1].u_wdf_data1/RDEN
                            (rising edge-triggered cell FIFO36E2 clocked by mmcm_clkout0_1  {rise@0.000ns fall@1.876ns period=3.752ns})
  Path Group:             mmcm_clkout0_1
  Path Type:              Setup (Max at Slow Process Corner)


Careful floorplanning can be used to resolve these timing failures.

However, in some cases floorplanning might not resolve the issue, in which case installing the attached tactical IP patch is required.

If you are still unable to resolve the timing failures please open a Service Request with Xilinx Technical Support.

To install the patch, extract the contents of "" to the 2014.4 install directory (for example, C:\Xilinx\Vivado\2014.4\), then open Vivado 2014.4 and regenerate all of your MIG UltraScale IP.

Note1: This tactical patch is only compatible with the Vivado 2014.4 and MIG UltraScale v6.1 IP.

Note2: Performance_NetDelay_high or Congestion_SpreadLogic_high implementation strategies might need to be applied to close timing with the provided patch.

Revision History:

01/16/2015 - Initial Release


文件名 文件大小 File Type 1 MB ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
69037 UltraScale/UltraScale+ RLDRAM3 - 发布说明与已知问题 N/A N/A
AR# 63238
日期 12/19/2017
状态 Active
Type 已知问题