AR# 6330

VCS - How do I compile Xilinx simulation libraries for VCS? (Verilog)

描述


General Description:

For VCS/VCSi, you might need to compile the HDL libraries before using them for design simulations. The advantages of the compiled approach are speed of execution and economy of memory.
AR# 6330
日期 03/31/2012
状态 Archive
Type 综合文章