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AR# 63345

JESD204 v6.0 PG066 Product Guide - Table 2-30 Error Reporting bits are swapped

描述

In (PG066), JESD204 v6.0, Table 2-30 contains the register description for the Error Reporting (RX Only) register:

63345-1.jpg

 

Bit 8 and bit 0 appear to be swapped when compared to the jesd204_0_block.v file.  

Which is correct?

解决方案

The file jesd204_0_block.v is correct.  

Table 2-30 in (PG066) should show the following:

63345-2.jpg


Disable Error Reporting using SYNC interface is bit 8.

Link Error Counters enable is bit 0.

This is corrected in v6.1 of the Product Guide, (PG066).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 63345
日期 04/30/2015
状态 Active
Type 综合文章
IP
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