AR# 63493


MIG 7 Series - ERROR when regenerating a remotely sourced MIG core in customers larger design


Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)

I add my MIG core remotely to my Vivado project, and then run Synthesis.

I receive the following errors in the OOC synthesis run for the MIG core, even though I had previously generated the MIG core and it is up-to-date:

Starting RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:22 . Memory (MB): peak = 309.398 ; gain = 144.738
INFO: [Synth 8-638] synthesizing module 'mig_7series_tst' [f:/DDR3_Store/IP/mig_7series_tst/mig_7series_tst/user_design/rtl/mig_7series_tst.v:69]
ERROR: [Synth 8-439] module 'mig_7series_tst_mig' not found [f:/DDR3_Store/IP/mig_7series_tst/mig_7series_tst/user_design/rtl/mig_7series_tst.v:148]
ERROR: [Synth 8-285] failed synthesizing module 'mig_7series_tst' [f:/1037356/DDR3_Store/IP/mig_7series_tst/mig_7series_tst/user_design/rtl/mig_7series_tst.v:69]
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 345.309 ; gain = 180.648


This issue can occur when using a remotely generated IP MIG core from a manage IP project which has a different language setting to the target project.

This causes the MIG IP to go out of date and to want to regenerate in the target project. 

This is expected behavior.

However, the regeneration does not complete for the MIG core due to the project language mis-match and as a result these errors are seen.

To work around the issue the following options are available:

  • Lock the IP in the target project.
  • Ensure both project have the same language setting.
  • Set the MIG core to be managed by the user, (i.e. IS_MANAGED property set to 0 for the MIG core).
  • Make the XCI file read only.

Revision History
102/02/2015 - Initial release 

AR# 63493
日期 03/23/2015
状态 Active
Type 综合文章
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