UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63596

UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1

描述

Version Found: v6.1

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3, See (Xilinx Answer 69037) for RLDRAM3

MIG UltraScale designs might fail with HOLD violations when using the new speed file in 2014.4.1.

Failures can been seen with the following configurations:

DDR3/DDR4 (Data widths >= 64 bits)

  • Speed grade 1 - 1866 Mbps and above designs
  • Speed grade 2 - 2133 Mbps and above designs

RLDRAM3 (All data widths)

  • Speed grade 1 - 1656 Mbps and above designs
  • Speed grade 2 - 1800 Mbps and above designs

解决方案

If one of the above configurations is being used in 2014.4.1 and HOLD violations are seen within the MIG IP then running "phys_opt_desgin" can resolve the issue.

Post-Place Phys Opt Design (phys_opt_design) can be enabled in the Project Settings under Implementation or can be run manually via the Tcl command "phys_opt_design".

If timing failures are still seen after running "phys_opt_design", check if the violations are the same as the ones identified in (Xilinx Answer 63698).

If not, please open a Service Request for additional assistance.

Revision History:

03/09/2015 - Initial Release

链接问答记录

主要问答记录

相关答复记录

AR# 63596
日期 12/19/2017
状态 Active
Type 已知问题
器件
IP
的页面