2. 技术支持
  3. AR# 6368: M1.5 Timing Analyzer - 1.5isp2: Exclude paths used with the "nets" option do not work.
  4. AR# 63680: Kintex UltraScale FPGA KCU105 Evaluation Kit KUCon-TRD04 Targeted Reference Design - Release Notes and Known Issues Master Answer Record

AR# 63680

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Kintex UltraScale FPGA KCU105 Evaluation Kit KUCon-TRD04 Targeted Reference Design - Release Notes and Known Issues Master Answer Record

描述

This answer record contains the Release Notes and Known Issues for the Kintex UltraScale FPGA KCU105 Evaluation Kit KUCon-TRD04 Targeted Reference Design (TRD). 

The purpose of this answer record is to help you to avoid running into issues when performing intended operations with the KUCon-TRD04 10GBASE-R Ethernet Targeted Reference Design.

解决方案

The KUCon-TRD04 10GBASE-R Ethernet TRD is developed on the Kintex UltraScale FPGA KCU105 Evaluation Kit, targeting the Kintex UltraScale XCKU0404-2FFVA1156E FPGA.

The TRD demonstrates connectivity between the 10G Ethernet PCS/PMA IP (10GBASE-R) and the 10G Ethernet MAC IP, and Traffic flow on this 10G Ethernet Channel.

The primary components of the TRD are:

  • 10G Ethernet PCS / PMA IP
  • 10G Ethernet MAC IP

Hardware Test Setup Requirements

The prerequisites to run and test the Base TRD are:

  • KCU105 Evaluation Kit with XCKU040-2FFVA1156E FPGA
  • 10GBASE-R Ethernet TRD Design files available from xilinx.com
  • USB cable, standard-A plug to micro-B plug (Digilent cable)
  • ATX power supply adapter

Software Requirements

The tools required to simulate KUCon-TRD04 are:

  • Vivado Design Suite 2014.4.1 or later
  • USB UART drivers (CP210x VCP drivers)
  • Tera Term terminal emulator
  • Java SE Runtime Environment 7
  • Ethernet Controller application GUI (included in the reference design zip file)


KUCon-TRD04 for Vivado 2016.2

  • Board
  • Silicon
    • The Kintex UltraScale KCU105 Evaluation Kit ships with production silicon.
  • Tools
    • (Xilinx Answer 52787) - Vivado - "ERROR: [Common 17-143] Path length exceeds 260-Byte maximum allowed by Windows"

KUCon-TRD04 for Vivado 2016.1

  • Board
  • Silicon
    • The Kintex UltraScale KCU105 Evaluation Kit ships with production silicon.
  • Tools
    • (Xilinx Answer 52787) - Vivado - "ERROR: [Common 17-143] Path length exceeds 260-Byte maximum allowed by Windows"

KUCon-TRD04 for Vivado 2015.4

  • Board
  • Silicon
    • The Kintex UltraScale KCU105 Evaluation Kit ships with production silicon.
  • Tools
    • (Xilinx Answer 52787) - Vivado - "ERROR: [Common 17-143] Path length exceeds 260-Byte maximum allowed by Windows"


KUCon-TRD04 for Vivado 2015.3
  • Board
  • Silicon
    • The Kintex UltraScale KCU105 Evaluation Kit ships with production silicon.
  • Tools
    • (Xilinx Answer 52787) - Vivado - "ERROR: [Common 17-143] Path length exceeds 260-Byte maximum allowed by Windows"

KUCon-TRD04 for Vivado 2015.2

  • Board
  • Silicon
    • The Kintex UltraScale KCU105 Evaluation Kit ships with production silicon.
  • Tools
    • (Xilinx Answer 52787) - Vivado - "ERROR: [Common 17-143] Path length exceeds 260-Byte maximum allowed by Windows"

KUCon-TRD04 for Vivado 2015.1

  • Board
  • Silicon
    • The Kintex UltraScale KCU105 Evaluation Kit ships with production silicon.
  • Tools
    • (Xilinx Answer 52787) - Vivado - "ERROR: [Common 17-143] Path length exceeds 260-Byte maximum allowed by Windows"


KUCon-TRD04 for Vivado 2014.4.1

  • Silicon
    • The Kintex UltraScale KCU105 Evaluation Kit ships with production silicon.
  • Tools
    • (Xilinx Answer 52787) - Vivado - "ERROR: [Common 17-143] Path length exceeds 260-Byte maximum allowed by Windows"

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
63175 Kintex UltraScale FPGA KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
64869 Kintex UltraScale FPGA KCU105 Evaluation Kit - ETH PHY link issues N/A N/A
AR# 63680
日期 11/03/2016
状态 Active
Type 综合文章
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