AR# 63689

UltraScale/UltraScale+ QDRII+ IP - Read Latency 2.0 (RL2) and Burst Length 2 (BL2) designs fail simulation with Cypress memory model

描述

Version Found: v7.0

Version Resolved: See (Xilinx Answer 69038)

For MIG UltraScale QDRII+ designs configured for Read Latency 2.0 (RL2) and Burst Length 2 (BL2), IES and VCS simulations can fail with data mismatch error messages coming from the Cypress memory model.

解决方案

This is a known issue with the CY7C2644KV18 and CY7C2542KV18 Cypress memory models.

Please contact Cypress directly to resolve this issue with their models.

Revision History:

02/24/2015 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69038 UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues N/A N/A
AR# 63689
日期 12/15/2017
状态 Active
Type 已知问题
器件 More Less
Tools
IP