AR# 63852

UltraScale DDR3 - Use of HR banks requires update of the output_impedance of all ports using reset_property command

描述

MIG UltraScale support for HR banks includes DDR3 interfaces only. 

Starting with Vivado 2015.1, I/O Pin Planning has moved from the MIG customization GUI to the Vivado I/O Pin Planner. 

With this change, at the time of MIG IP generation, the I/O column (HP versus HR) is not known. 

As the majority of memory interface designs are located in HP banks, the output impedance required for HR banks is not set. 

Manual modifications are required and detailed within this answer record.

解决方案

For HR banks, you will have to update the output_impedance of all of the ports assigned to HR banks pins using the reset_property command as follows:

reset_property OUTPUT_IMPEDANCE [get_ports [list <MIG port list> ]] 

Failure to reset the output_impedance will result in the following errors during Place:

ERROR: [DRC 23-20] Rule violation (PORTPROP-9) Attribute compatibility with bank type - Port c0_ddr3_addr[0] has property OUTPUT_IMPEDANCE set, but this property is not compatible with the port's bank type (High Range)

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 63852
日期 01/12/2018
状态 Active
Type 综合文章
器件
Tools
IP