AR# 63859

MIG - 7 Series - LPDDR2 - Simulation errors seen when simulating a MIG design

描述

Version Found: MIG 7 Series v2.1
Version Resolved: See (Xilinx Answer 54025)


I am receiving the following errors when simulating a MIG design with the default settings:

sim_tb_top.mem_rnk[0].gen_mem[0].u_comp_lpddr2.ERROR at time 435261000: Nop or Deselect must be driven in the clock cycle after CKE goes l
sim_tb_top.mem_rnk[0].gen_mem[0].u_comp_lpddr2.ERROR at time 867261000: Nop or Deselect must be driven in the clock cycle after CKE goes low

sim_tb_top.mem_rnk[0].gen_mem[0].u_comp_lpddr2.ERROR at time 3503921000: tINIT3 violation


解决方案

These errors can be safely ignored and will be fixed in MIG v2.3 Rev1.

Revision History:
03/11/2015 - Initial Release

链接问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 63859
日期 03/12/2015
状态 Active
Type 综合文章
Tools