AR# 63987

Simulation - How to run functional simulation using Vivado Simulator?


You can perform functional simulation after synthesis or implementation.

It allows you to ensure that the synthesized or implemented design meets the functional requirements and behaves as expected.

This article describes the two ways to run functional simulation using Vivado Simulator: from the Vivado IDE and from the command line.


Vivado IDE:

  1. In your Vivado project, run synthesis or implementation.
  2. Specify Vivado Simulator Simulation Settings if necessary.
  3. From the Flow Navigator, select
    Run Simulation > Run Post-Synthesis Functional Simulation

    Run Simulation > Run Post-Implementation Functional Simulation.
    The option becomes available only when synthesis or implementation is run successfully.



Command Line:

1) Generate a functional simulation netlist. 

The functional simulation netlist is a hierarchical, folded netlist that is expanded to the primitive module or entity level. The lowest level of hierarchy consists of primitives. 

The following Tcl commands take a synthesized or implemented design database and write out a single netlist for the entire design.


        open_checkpoint top.dcp
        write_verilog -mode funcsim top_funcsim.v (For Verilog)
        write_vhdl -mode funcsim top_funcsim.vhd (For VHDL)

Warning: Running the write_verilog command in a Synthesis post.tcl script will not work properly if the design contains IP modules with output products generated as out of context (OOC) modules. 

The synthesis process will not have access to these OOC modules and will see them as black boxes. The correct option in this case would be to open the synthesized design (loads the design from the project level) and then run write_verilog.

2) In many cases, you can use the same test bench that you used for behavioral simulation to perform a more accurate simulation.

As in behavioral simulation, either parse the individual files or a project file, elaborate and generate a snapshot, and then simulate.


        xvlog top_funcsim.v
        xvlog testbench.v
        xvlog $XILINX_VIVADO/data/verilog/src/glbl.v
        xelab -debug typical -L secureip -L unisims_ver testbench glbl -s top_funcsim
        xsim top_funcsim -gui

For more information on using Vivado Simulator and the command line options, please refer to (UG900) Vivado Design Suite User Guide: Logic Simulation.;d=ug900-vivado-logic-simulation.pdf



Answer Number 问答标题 问题版本 已解决问题的版本
58878 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Functional Simulation N/A N/A
AR# 63987
日期 09/29/2016
状态 Active
Type 综合文章