Simulation with the Vivado simulator happens in two phases:
- In the first phase, the simulator compiler xelab, compiles the HDL model into a snapshot, which is a representation of the model in a form that the simulator can execute.
- In the second phase, the simulator simulates the model by loading the snapshot and executing it (using the xsim command).
In Non-Project Mode, I can reuse the snapshot by skipping the first phase and repeating the second.
In Project Mode, each time I select Run Simulation, the simulation will start from compilation, even if a snapshot has been built before.
How do I skip compilation or simulation in the project-mode simulation flow?
You can skip the compilation through xelab and/or simulation through the Vivado simulator, using the following:
set_property skip_compilation 1 [get_filesets sim_1]
The Vivado tools will skip the compilation step of Vivado simulator and runs simulation with the existing compiled result.
Note: Any change to design files after the last compilation is not reflected in simulation when you set this property.
set_property skip_simulation 1 [get_filesets sim_1]
The Vivado tools will skip the execution of simulation step.
You can query all of the simulation fileset properties by using the below Tcl command:
report_property -all [get_filesets sim_1]