AR# 64006

UltraScale/UltraScale+ QDRII+ IP - Unexpected DRC for correct placement of memory clock pair (K/K#)

描述

Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 69038)

Unexpected DRC violations can be displayed for K[1] even when following the MIG Memory Clock (K/K#) allocation rules as follows:

  • Memory Clock pair must be allocated in one of the byte lanes that are used for the write data of the corresponding memory component.
  • Memory clock should come from one of the center byte lanes (byte lanes 1 & 2).
  • K/K# can be allocated to any PN pair.

解决方案

If the MIG Memory Clock allocation rules are being followed, then this violation is safe to ignore.

Revision History:

04/15/2015 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69038 UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues N/A N/A
AR# 64006
日期 12/15/2017
状态 Active
Type 已知问题
器件 More Less
Tools
IP