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AR# 64021

Vivado Synthesis - RAM not inferred when "wait until" is used for clock

描述

When I use the following HDL to describe a RAM, the code does not infer any RAM in Vivado, but instead only infers registers:

    G1: for i in D'range generate
        process
        begin
        wait until CLK = '1';
            if (CEN = '0')  then
                if  (GWEN = '0') and (WEN(i) = '0') then
                    mem(to_integer(unsigned(A)))(i) <= D(i);
                end if;
                Q(i) <= mem(to_integer(unsigned(A)))(i);
            end if;
        end process;
    end generate;

解决方案

The "wait until" statement is not supported for RAM inference.

Use the following statement instead:

if rising_edge(CLK)
or
if (CLK'event and CLK = '1')
AR# 64021
日期 04/08/2015
状态 Active
Type 已知问题
Tools
的页面