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AR# 64053

Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries - UNIFAST

描述

This Answer Record contains child answer records covering UNIFAST Xilinx Simulation Libraries.

The answer records provide explanations of the issues you might encounter when using UNIFAST Xilinx Simulation Libraries.

The answer record also contains information related to known issues and good coding practices.

Note: This article is part of Xilinx Simulation Solution Center (Xilinx Answer 58795)

The Xilinx Simulation Solution Center is available to address all questions related to Simulation.

Whether you are starting a new design with Vivado Simulator or troubleshooting a problem with a supported third party simulator, use the Xilinx Simulation Solution Center to guide you to the right information.

解决方案

(Xilinx Answer 64061) - Using Vivado Simulation Libraries - UNIFAST
(Xilinx Answer 59599) - Vivado Simulator FAQ - How do I speed up simulation?
(Xilinx Answer 62795) - Vivado 2014.3 and later - BRAM and FIFO UNIFAST models have been removed
(Xilinx Answer 62957) - 2014.3 OTN IP simulations producing ERROR: (vcom-1129) Type mismatch for generic "IS_CLKRSVD0_INVERTED" of component "GTHE2_CHANNEL" when binding to entity "GTHE2_CHANNEL".

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58801 Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries N/A N/A

子答复记录

AR# 64053
日期 05/20/2015
状态 Active
Type 解决方案中心
Tools
的页面