AR# 64089

Aurora Design Assistant - Design Implementation


The Aurora Design Assistant walks you through the recommended design flow for Aurora 8B10B/ Aurora 64B66B designs while debugging commonly encountered issues, such as simulation issues, initialization failures, and data errors.

The Design Assistant provides useful design and troubleshooting information, but also points you to the exact documentation you need to read to help you design efficiently with Aurora 8B10B/Aurora 64B66B.

Note: This Answer Record is a part of the Xilinx Aurora Solution Center (Xilinx Answer 21263).

The Xilinx Aurora Solution Center is available to address all questions related to Aurora 8B10B/Aurora 64B66B.

Whether you are starting a new design with Aurora or troubleshooting a problem, use the Aurora Solution Center to guide you to the right information.


  • Ensure that the .xdc constraints are complete.
    If .xci files are not used in design implementation, constraints present in core level .xdc files needs to be copied to the master .xdc of the design.

  • The IP has covered all CDC paths using synchronizers.
    As a result, there are no clock to clock constraints.
    Please do not add clock to clock constraints to analyze these paths.
    CDC paths in user design need to be taken care of independently.

  • Please ensure the skew between the lanes is within the allowable limits of the IP:
    • For Aurora 64B66B, this is 132UI
    • For Aurora 8B10B, it is 7 RXUSRCLK cycles
  • Reset requirements for the core should be implemented as per the Product Guide recommendation.
    Reset sequence implementation is present in the example design for Aurora 64B66B.

  • For Artix-7 GTP based designs, Aurora 8B10B implements the GTP reset sequence recommendation for production silicon as mentioned in (Xilinx Answer 53561).
    This reset circuit is implemented using DRP operations.
    It is mandatory to provide DRP_CLK input to Aurora 8B10B designs targeting Artix-7 GTP.

  • You should always check the GT attributes in the core with respect to GT wizard output as it will have the latest attribute settings for better GT performance.
    For UltraScale cores, the GT wizard is called as a sub-core by the Aurora cores, so the attributes are expected to be up to date.

  • INIT_CLK input must be provided.
    Ensure the guidelines from the product guide are followed.

  • It is always recommended to match the STABLE_CLK_PERIOD attribute value to the period of INIT_CLK input from the hardware.
    From the Vivado 2014.1 release, this is taken care of in the core, since the INIT_CLK frequency is requested when the core is generated.

  • If INIT_CLK is generated from MMCM, ensure the reset inputs are held HIGH until INIT_CLK is stable.

  • Assign the following auxiliary signals to "GND" if they are unused.
    (For details about functionality of the following signals, please refer to the Product Guide).
  1. loopback
  2. power down

  • Leave the following signals unconnected, if they are unused:

    DRP outputs (DRPRDY)

  • For Simplex designs, set the "timer" values as per the recommendation from the Product Guide
    • Aurora 64B66B -- SIMPLEX_TIMER_VALUE in Simplex Tx core
    • Aurora 8B10B -- C_ALIGNED_TIMER, C_BONDED_TIMER, and C_VERIFY_TIMER in Simplex Tx core
  • When Aurora cores are instantiated multiple times and alternate clock buffers are required to be used, the same type of clock buffers must be used for both USER_CLK and SYNC_CLK.
    Please refer to (Xilinx Answer 60697) for more details.

  • For UltraScale cores, you must update the top level .xdc file with the LOC constraint of the GT REFCLK input.

  • If the REFCLK input is routed from adjacent quads which are not used by Aurora, updating the LOC constraint in .xdc will ensure that the clock is routed as required.



Answer Number 问答标题 问题版本 已解决问题的版本
61912 Aurora Solution Center - Design Assistant N/A N/A
AR# 64089
日期 08/11/2015
状态 Active
Type 解决方案中心