AR# 64091

Aurora Design Assistant - Simulation


The Aurora Design Assistant walks you through the recommended design flow for Aurora 8B10B/ Aurora 64B66B designs while debugging commonly encountered issues, such as simulation issues, Initialization failures, and data errors.

The Design Assistant provides useful design and troubleshooting information, but also points you to the exact documentation you need to read to help you design efficiently with Aurora 8B10B/Aurora 64B66B.

Note: This Answer Record is a part of the Xilinx Aurora Solution Center (Xilinx Answer 21263).

The Xilinx Aurora Solution Center is available to address all questions related to Aurora 8B10B/Aurora 64B66B.

Whether you are starting a new design with Aurora or troubleshooting a problem, use the Aurora Solution Center to guide you to the right information.


  • It is recommended to start with simulation of the IP example design to confirm the IP functionality.

  • For Artix-7 GTP and Virtex-7 GTH based designs, Aurora 8B10B implements the reset sequence recommendation for production silicon as mentioned in (Xilinx Answer 53561) and (Xilinx Answer 53779).
    This reset circuit is implemented using DRP operations.
    As a result, it is mandatory to provide DRP_CLK input to Aurora 8B10B designs targeting Artix-7 GTP (or) Virtex-7 GTH.
    Simulation needs to run for around 1.3ms for single lane design.
    This is because the SPEEDUP parameter for the GT model cannot be set.

  • Set USE_CHIPSCOPE/USE_LABTOOLS  to "0" for simulation purpose (Until Vivado 2014.2). 

  • Please refer to the Xilinx Simulation Solution Center (Xilinx Answer 58795) for more guidance with any simulator specific issue.

  • Refer to the Vivado tutorials site and check the quick take videos under "Design Analysis" for the steps to simulate using different simulators(Cadence IES, Synopsys VCS, Mentor Questa etc.) in Vivado.



Answer Number 问答标题 问题版本 已解决问题的版本
61912 Aurora Solution Center - Design Assistant N/A N/A
AR# 64091
日期 07/01/2015
状态 Active
Type 解决方案中心