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3.1i FPGA Editor - When adding probes to Virtex, the banking information is required.
Keywords: Bank, I/O, IO, pin, component, 2.1i
When I add a probe to a Virtex design, the I/O banking information is not used, and the particular I/O is left unchecked.
To work around this, check the correct box for the particular IOB, depending upon the I/O standard that is in that bank.
This will be fixed in a future software release.