AR# 64146

UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie parts

描述

Version Found: DDR3 v7.0

Version Resolved: See (Xilinx Answer 69036)

When running behavioral simulations for 16Gb and 8Gb DDR3 TwinDie parts (i.e. MT41K1G16DGA-125, MT41K1G16DGA-125 etc.) the following warnings are received:

# ** Warning: (vsim-3015) ./../../../mig_5_example.srcs/sim_1/imports/tb/sim_tb_top.sv(417): [PCDPC] - Port size (15) does not match connection size (16) for port 'addr'. The port definition is at: ./../../../mig_5_example.srcs/sim_1/imports/tb/ddr3_model/ddr3.v(101).
#         Region: /sim_tb_top/mem_model_x16/mem/memRank[0]/memModel[0]/u_ddr3_x16
# ** Warning: (vsim-3015) ./../../../mig_5_example.srcs/sim_1/imports/tb/sim_tb_top.sv(417): [PCDPC] - Port size (15) does not match connection size (16) for port 'addr'. The port definition is at: ./../../../mig_5_example.srcs/sim_1/imports/tb/ddr3_model/ddr3.v(101).

解决方案

This is a result of Micron not having 16Gb or 8Gb memory models available for simulation.

Due to no memory model being available, MIG automatically sets the density to 4Gb for the test bench and memory model only so that behavioral simulations can still be run.

As a result there are only 15 address bits connected which results in the warning messages.

These warning messages can be safely ignored and no work-around is needed.

Please check with Micron on availability of 8Gb models.

Revision History:

04/15/2015 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 64146
日期 01/08/2018
状态 Active
Type 已知问题
器件
Tools
IP