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AR# 64569

KC705 User Guide UG810 (v1.6.1) - USB UART pin constraints in UG810 do not match Vivado 2015.1 “part0_pins.xml” board file

描述

In the current Kintex-7 FPGA KC705 Evaluation Kit User Guide, (UG810) v1.6.1, the Appendix C XDC Constraints File Listing shows the following:

 

64569-1.jpg





However, in the Vivado install folder on the user PC (default path indicated below), the pin constraint file of the KC705 board shows the USB UART pin assignments to be:

 

 

pin index="93" name ="USB_CTS" iostandard="LVDS" loc="L27"
pin index="94" name ="USB_TX" loc="K24"
pin index="95" name ="USB_RX" loc="M19"
pin index="96" name ="USB_RTS" iostandard="LVCMOS25" loc="K23"

 

(C:\Xilinx\Vivado\2015.1\data\boards\board_files\kc705\1.2\part0_pins.xml)

Note: for pin index 94 & 95 IOSTANDARD is defined in component rs232_uart

IOSTANDARD is an optional attribute for FPGA pins and it will be always be overwritten by component (non FPGA) level pin attributes.

 

The (UG810) xdc listings for USB_TX and USB_RX pin assignment constraints do not match those in the part0_pins.xml file.


In (UG810) appendix C, the USB_TX pin is M19 and the USB_RX pin is K24.

 
In the part0_pins.xml file, the USB_TX pin is K24 and the USB_RX pin is M19.

解决方案

The axi_uartlite IP implements only the TX and RX ports, so the RTS and CTS pins on the FPGA are not used.

The net names shown in the KC705 hardware documentation posted on xilinx.com are matching and are named from the perspective of the USB UART CP2103 component function.
 
  • KC705 UG810 hardware user guide: ug810_KC705_Eval_Bd.pdf
  • KC705 schematic:  kc705_Schematic_xtp132_rev1_1.pdf
  • KC705 xdc file: kc705-ucf-xdc-rdf0150-rev1-0.zip (KC705_Rev1_0_U1.ucf.xdc)
 
 
From Table 1-20 in (UG810), note the Function columns:
64569-2.jpg




 
Therefore the schematic net named USB_TX is wired to FPGA U1 pin M19 but the FPGA IP axi_uartlite function of this pin M19 is RX.

Similarly, the schematic net named USB_RX is wired to FPGA U1 pin K24 but the FPGA IP axi_uartlite function of this pin K24 is TX.
 
The constraints in the part0_pins.xml file are named from the perspective of the axi_uartlite IP in the FPGA, hence they are the reverse of the hardware document naming perspective.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 64569
日期 06/09/2015
状态 Active
Type 综合文章
器件
  • Kintex-7
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit
的页面