AR# 64600

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LogiCORE IP G.709 FEC Encoder/Decoder v2.1(Rev. 5) - A setup timing violation may occur if Encoder implementation is set to BALANCED or DSP BIAS

描述

If the target device is a Virtex UltraScale speed grade -2 part, and if the IP parameter "Encoder implementation" is set to BALANCED or DSP BIAS, a timing error can occur.

This manifests as a negative slack violation of a setup timing constraint.

解决方案

The work-around is to set "LUT_BIAS" for the "Encoder implementation" parameter, or to use a Virtex UltraScale speed grade -3 part.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54477 LogiCORE IP G.709 FEC Encoder/Decoder - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 64600
日期 05/28/2015
状态 Active
Type 综合文章
器件
Tools
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