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AR# 64642

UltraScale RLDRAM3 - IP upgrade in 2015.1 creates DDR4 controller

描述

Version Found: RLDRAM3 v7.0

Version Resolved: See (Xilinx Answer 69037)

When migrating a MIG UltraScale RLDRAM3 IP to 2015.1, a DDR4 controller can mistakenly be created instead of RLDRAM3.

This only occurs when the "sys_rst" port is not assigned to an I/O site in the original MIG UltraScale RLDRAM3 IP.

解决方案

If this issue occurs you must regenerate a new MIG UltraScale RLDRAM3 IP in Vivado 2015.1 to ensure that the proper interface type and the rest of the IP parameters are generated properly.

See (Xilinx Answer 63831) for guidance on Migrating and Upgrading IP into 2015.1.

Revision History:

05/21/2015 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69037 UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
63831 MIG UltraScale - Migrating and Upgrading IP into 2015.1 N/A N/A
AR# 64642
日期 12/19/2017
状态 Active
Type 已知问题
器件
Tools
IP
的页面