AR# 64772

UltraScale RLDRAM3 - timing failures in mmcm_clk0 domain as a result of too many logic levels

描述

Version Found: RLDRAM3 v7.1

Version Resolved: See (Xilinx Answer 69037)

The following path (or similar paths) might fail timing for MIG UltraScale RLDRAM3 designs as a result of too many logic levels:

Slack (VIOLATED) : -0.370ns (required time - arrival time)
Source: u_SN33_kintexuRLDRAM3_933MHz_36bit_vivado_ssit/inst/u_rld3_mem_intfc/u_rld_mc/start_idx_reg[0]/C
(rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@2.142ns period=4.284ns})
Destination: u_SN33_kintexuRLDRAM3_933MHz_36bit_vivado_ssit/inst/u_rld3_mem_intfc/u_rld_ui/usr_addr_fifo/u_af1.u_af/RDEN
(rising edge-triggered cell FIFO36E2 clocked by mmcm_clkout0 {rise@0.000ns fall@2.142ns period=4.284ns})
Path Group: mmcm_clkout0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.284ns (mmcm_clkout0 rise@4.284ns - mmcm_clkout0 rise@0.000ns)
Data Path Delay: 3.393ns (logic 1.076ns (31.712%) route 2.317ns (68.288%))
Logic Levels: 6 (LUT2=1 LUT3=1 LUT6=4)
Clock Path Skew: -0.188ns (DCD - SCD + CPR)

解决方案

To work around this issue, try using a number of different implementation strategies (for example, register balancing, retiming, etc.).

If the user logic is being driven by the mmcm_clk domain try inserting an additional BUFG for the user logic to allow Vivado to properly balance the user and MIG domain.

If these violations are still seen please open a Service Request for assistance:

https://www.xilinx.com/support/service-portal.html

Revision History:

06/30/2015 - Initial Release

07/06/2015 - Updated solution

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69037 UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues N/A N/A
AR# 64772
日期 12/19/2017
状态 Active
Type 已知问题
器件
Tools
IP