Version Found: RLDRAM3 v7.1
Version Resolved: See (Xilinx Answer 69037)
The following path (or similar paths) might fail timing for MIG UltraScale RLDRAM3 designs as a result of too many logic levels:
To work around this issue, try using a number of different implementation strategies (for example, register balancing, retiming, etc.).
If the user logic is being driven by the mmcm_clk domain try inserting an additional BUFG for the user logic to allow Vivado to properly balance the user and MIG domain.
If these violations are still seen please open a Service Request for assistance:
06/30/2015 - Initial Release
07/06/2015 - Updated solution